The invention relates to an information carrier including a pattern of substantially parallel tracks, each track including a plurality of sectors and each sector including an address information area and an associated data area, the data area being a continuation of the address information area and the address information area including at least one address information field and at least one synchronization field, and the address information areas in adjacent tracks overlapping each other, the address information fields in overlapping address information areas being positioned free from overlap relative to each other.
The invention further relates to an apparatus for reading the information carrier, including an optical system for detecting optically readable signs by generating a light spot on the information carrier, a tracking unit for controlling the position of the light spot and a reading unit for reading the address information.
An information carrier and apparatus of this type are known, for example, from Japanese patent application JP 09237473 A, (document D1). This document describes an information carrier which includes address information areas, the so-called headers, and data areas and an apparatus. The address information areas belong to and are continuations of the data areas directly following these address information areas. These address information areas include address information fields which are fields containing address information, and synchronization fields which are fields providing that a phase-locked loop (PLL) can synchronize a clock signal on the basis of optically readable signs on the information carrier. In this manner the address information fields can be read. The synchronization fields provide a reliable synchronization before information in the form of address information fields or data fields is read or written. For the signals to be strong enough when the address information areas are read, these areas are placed in line with the data areas. The headers are distributed over the various tracks present on the information carrier. The whole is also called the header structure.
Document D1 explains that, after each field containing synchronization fields and address information fields, hereinafter called sync/address field, one field is left empty. This is done to reduce the danger of address information fields of adjacent tracks being detected as a result of crosstalk. These sync/address fields occur in address information areas overlapping adjacent address information areas. A field that is left empty contains neither synchronization fields nor address information fields. As such a field is left empty, the dimensions of the address information areas are increased and this detrimentally affects the total storage capacity of the information carrier.
Those skilled in the art should refer to U.S. pat. No. 5,383,176 (Document D2).
The above references are hereby incorporated in the whole by reference.
It is an object of the invention to provide such a header structure that a larger storage capacity of the information carrier can be reached, while a reliable reading of the address information is possible.
For this purpose, an information carrier as described in the opening paragraph according to the invention has synchronization fields in overlapping address information areas, overlap the address information fields.
By having the adjacent synchronization fields overlap, a more compact header structure is reached than the structure known from document D1. As a result of this more compact structure, the headers on the information carrier take up less space, so that more room is left for the data areas. This achieves a larger capacity of this information carrier.
The invention is based inter alia on the recognition that the crosstalk as a result of the synchronization fields is less than the crosstalk as a result of the address information fields. The synchronization field, for that matter, contains in essence relatively short marks, so that a relatively high frequency signal is generated for synchronizing the clock signal. Such relatively short marks cause less crosstalk than relatively long marks which occur in the address information field and generate a relatively low frequency signal. This provides the possibility of positioning the address information fields beside the synchronization fields in the adjacent tracks and providing a reduction of the size of the header while maintaining a reliable header detection.
The reason for relatively short marks causing less crosstalk than relatively long marks will be explained as follows. When a track is read out, also the adjacent track provides a contribution to the reading signal because the dimension of the laser beam is larger than the width of the track to be read out. In the case where relatively short marks occur in this track, the contribution of these marks to the total reading signal will be smaller than in the case where there are relatively long marks in the track. This is caused, on the one hand, by the fact that small marks simply provide less modulation. On the other hand, this little modulation is further mitigated because the effective spot-size in the adjacent track is larger than in the track to be read out.
Another header structure is known from United States patent U.S. Pat. No. 5,383,176, (document D2). The reduction of the header that is realized in this case is, however, smaller than the reduction of the header realized in the header structure described here. In document D2, part of the header is placed in the land/groove area as a result of which, as is known, a reduction of the crosstalk is obtained by the use of lands and grooves. A disadvantage of this header structure is the fact that because part of the header is placed in the land/groove area, the reading signals of the header in the land/groove area deviate from the reading signals of the header in the rest of the header. This complicates the detection.
In a further embodiment the address information areas contain at least two address information fields and at least two synchronization fields, the address information fields and the synchronization fields being arranged alternately.
By composing an address information field in this manner, it is possible to render the address information available twice in a compact structure. Compared with document D1, this structure results in a size reduction of 37.5% in the case where there are two address information fields and two synchronization fields of equal size. Since the synchronization fields are generally larger than the address information fields, the reduction will be even higher.
In a further embodiment the address information areas in the two tracks adjacent to a track have an identical subdivision of address information fields and synchronization fields.
In a further embodiment the address information areas have a subdivision in which the synchronization fields in the two tracks lying adjacent to a track are substantially in identical positions.
These previous two embodiments are advantageous in that the information carrier carries only a limited number of different types of address information areas. As a result, it is possible for the address information available in the address information areas to be read out in a simple and reliable manner. In addition, the manufacturing of information carriers having space reserved for the address information areas is simplified.
In a further embodiment the synchronization fields in the tracks adjacent to the track to be read out have a mutual shift of the order of several bits.
In a further embodiment the shift of synchronization fields in the two tracks adjacent to the track to be read out is so large that pits in one track adjacent to the track to be read out correspond to spaces in the other track adjacent to the track to be read out. Spaces in this case are meant to be understood as the areas between the pits.
These previous two embodiments are advantageous in that the crosstalk is even further reduced. Since the synchronization fields in the tracks adjacent to the track to be read out have a mutual shift of the order of several bits. the signals coming from the tracks adjacent to the track to be read out cancel each other out. This further reduces the crosstalk.
According to a second aspect of the invention. an apparatus as defined in the opening paragraph includes a detector means for detecting the length of the synchronization fields.
The apparatus is advantageous in that, as the length of the synchronization fields is known, the reading of the address information fields can be started at the right moment. As a result, the chance is made slimmer that part of the address information area is mistaken for an address information field. The robustness of the header detection is increased as a result of this. Besides, knowing the length of the synchronization fields can be used for varying the properties of the detection of the signal coming from the information carrier.
These and other aspects of the invention are apparent from and will be elucidated by the detailed description of embodiments below with reference to the following drawings.